1. Field
The present disclosure generally relates to clocking circuits. More specifically, the present disclosure relates to a clock-adjustment circuit that adjusts the relative phase of a clock at a clock-domain boundary to reduce the latency of a first-in first-out (FIFO) buffer.
2. Related Art
Serializer/deserializer (SerDes) circuits are often used as input/output (I/O) circuits. In such applications, there are typically two clocks: the receiver recovered clock (RRCLK) and a core logic clock (CCLK).
CCLK is typically generated using a reference that has a fixed phase and a fixed frequency. RRCLK is usually recovered from received data using a clock-data recovery (CDR) circuit, and has a phase and a frequency that follow the sampled data. However, there may be a random phase contribution to the phase of the received data (for example, because of clock latency, phase jitter and/or propagation delays in signal lines). As a consequence, for the same received data, the phase of RRCLK may be random relative to that of the reference clock that was used to transmit the data. If the reference clock is shared with the core logic, this randomness can cause RRCLK and CCLK to have a different and random phase, even though they have the same frequency.
Moreover, when data is passed from the RRCLK clock domain to the CCLK clock domain, a first-in first-out (FIFO) buffer is typically used. However, the randomness of the relative phases of RRCLK and CCLK can significantly increase the latency cost in the datapath, which can degrade the performance of the entire design.
Hence, what is needed is a clock-adjustment circuit for use in conjunction with clock-domain boundaries to convert the random phase relationship between the RRCLK and CCLK into fixed/targeted relationship to enable using low latency FIFO design for determined read and write clock.